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» Process variation aware clock tree routing
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IS
2011
13 years 2 months ago
Optimized query routing trees for wireless sensor networks
In order to process continuous queries over Wireless Sensor Networks (WSNs), sensors are typically organized in a Query Routing Tree (denoted as T) that provides each sensor with ...
Panayiotis Andreou, Demetrios Zeinalipour-Yazti, A...
FPGA
2004
ACM
121views FPGA» more  FPGA 2004»
14 years 24 days ago
Highly pipelined asynchronous FPGAs
We present the design of a high-performance, highly pipelined asynchronous FPGA. We describe a very fine-grain pipelined logic block and routing interconnect architecture, and sh...
John Teifel, Rajit Manohar
SENSYS
2009
ACM
14 years 2 months ago
Integrated distributed energy awareness for wireless sensor networks
Energy in sensor networks is a distributed, non-transferable resource. Over time, differences in energy availability are likely to arise. Protocols like routing trees may concent...
Geoffrey Werner Challen, Jason Waterman, Matt Wels...
FPGA
2010
ACM
250views FPGA» more  FPGA 2010»
14 years 4 months ago
Variation-aware placement for FPGAs with multi-cycle statistical timing analysis
Deep submicron processes have allowed FPGAs to grow in complexity and speed. However, such technology scaling has caused FPGAs to become more susceptible to the effects of process...
Gregory Lucas, Chen Dong, Deming Chen
MICRO
2003
IEEE
166views Hardware» more  MICRO 2003»
14 years 20 days ago
Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation
With increasing clock frequencies and silicon integration, power aware computing has become a critical concern in the design of embedded processors and systems-on-chip. One of the...
Dan Ernst, Nam Sung Kim, Shidhartha Das, Sanjay Pa...