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» Processor Architectures for Ontogenesis
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ISSS
2002
IEEE
174views Hardware» more  ISSS 2002»
15 years 9 months ago
A Run-Time Word-Level Reconfigurable Coarse-Grain Functional Unit for a VLIW Processor
Nowadays, new DSP applications are offering combined and flexible multimedia and telecom services. VLIW processor architectures, which include dedicated but inflexible functional ...
Carles Rodoreda Sala, Natalino G. Busá
ASAP
2004
IEEE
127views Hardware» more  ASAP 2004»
15 years 8 months ago
A Public-Key Cryptographic Processor for RSA and ECC
We describe a general-purpose processor architecture for accelerating public-key computations on server systems that demand high performance and flexibility to accommodate large n...
Hans Eberle, Nils Gura, Sheueling Chang Shantz, Vi...
VLSISP
2008
123views more  VLSISP 2008»
15 years 4 months ago
Implementation of a Coarse-Grained Reconfigurable Media Processor for AVC Decoder
ADRES (Architecture for Dynamically Reconfigurable Embedded Systems) is a templatized coarse-grained reconfigurable processor architecture. It targets at embedded applications whic...
Bingfeng Mei, Bjorn De Sutter, Tom Vander Aa, M. W...
RECONFIG
2008
IEEE
184views VLSI» more  RECONFIG 2008»
15 years 10 months ago
FPGA Implementation of an Elliptic Curve Cryptosystem over GF(3^m)
This paper describes an efficient arithmetic processor for elliptic curve cryptography. The proposed processor consists of special architectural components, the most important of...
Ilker Yavuz, Siddika Berna Ors Yalcin, Çeti...
SAMOS
2009
Springer
15 years 11 months ago
Runtime Adaptive Extensible Embedded Processors - A Survey
Current generation embedded applications demand the computation engine to offer high performance similar to custom hardware circuits while preserving the flexibility of software s...
Huynh Phung Huynh, Tulika Mitra