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» Processor Architectures for Ontogenesis
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FPL
2005
Springer
125views Hardware» more  FPL 2005»
15 years 10 months ago
Low-Cost Fully Reconfigurable Data-Path for FPGA-Based Multimedia Processor
This paper describes novel data-path architecture for FPGA-based multimedia processors. The proposed circuit can adapt itself at run-time to different operations and data wordleng...
Marco Lanuzza, Stefania Perri, Martin Margala, Pas...
WADS
2005
Springer
132views Algorithms» more  WADS 2005»
15 years 10 months ago
Communication-Aware Processor Allocation for Supercomputers
Abstract. We give processor-allocation algorithms for grid architectures, where the objective is to select processors from a set of available processors to minimize the average num...
Michael A. Bender, David P. Bunde, Erik D. Demaine...
DATE
2003
IEEE
87views Hardware» more  DATE 2003»
15 years 9 months ago
FPGA-Based Implementation of a Serial RSA Processor
In this paper we present an hardware implementation of the RSA algorithm for public-key cryptography. The RSA algorithm consists in the computation of modular exponentials on larg...
Antonino Mazzeo, Luigi Romano, Giacinto Paolo Sagg...
ISCAS
2003
IEEE
91views Hardware» more  ISCAS 2003»
15 years 9 months ago
Real-time implementation of H.263+ using TI TMS320c6201 digital signal processor
In this paper, we use a digital signal processor (DSP) to implement a real-time H.263+ codec. We use fast algorithms to reduce the codec computational complexity. Furthermore, the...
Timothy K. Shih, Chia-Yang Tsai, Hsueh-Ming Hang
SBACPAD
2003
IEEE
75views Hardware» more  SBACPAD 2003»
15 years 9 months ago
The Limits of Speculative Trace Reuse on Deeply Pipelined Processors
Trace reuse improves the performance of processors by skipping the execution of sequences of redundant instructions. However, many reusable traces do not have all of their inputs ...
Maurício L. Pilla, Amarildo T. da Costa, Fe...