This paper describes novel data-path architecture for FPGA-based multimedia processors. The proposed circuit can adapt itself at run-time to different operations and data wordleng...
Marco Lanuzza, Stefania Perri, Martin Margala, Pas...
Abstract. We give processor-allocation algorithms for grid architectures, where the objective is to select processors from a set of available processors to minimize the average num...
Michael A. Bender, David P. Bunde, Erik D. Demaine...
In this paper we present an hardware implementation of the RSA algorithm for public-key cryptography. The RSA algorithm consists in the computation of modular exponentials on larg...
Antonino Mazzeo, Luigi Romano, Giacinto Paolo Sagg...
In this paper, we use a digital signal processor (DSP) to implement a real-time H.263+ codec. We use fast algorithms to reduce the codec computational complexity. Furthermore, the...
Trace reuse improves the performance of processors by skipping the execution of sequences of redundant instructions. However, many reusable traces do not have all of their inputs ...