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» Processor Architectures for Ontogenesis
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146
Voted
CF
2005
ACM
15 years 6 months ago
An efficient wakeup design for energy reduction in high-performance superscalar processors
In modern superscalar processors, the complex instruction scheduler could form the critical path of the pipeline stages and limit the clock cycle time. In addition, complex schedu...
Kuo-Su Hsiao, Chung-Ho Chen
ISCAS
2008
IEEE
109views Hardware» more  ISCAS 2008»
15 years 11 months ago
A low-area interconnect architecture for chip multiprocessors
— A new inter-processor communication architecture for chip multiprocessors is proposed which has a low area cost and flexible routing capability. To achieve a low area cost, th...
Zhiyi Yu, Bevan M. Baas
113
Voted
HPCC
2007
Springer
15 years 10 months ago
Parallel Performance Prediction for Multigrid Codes on Distributed Memory Architectures
We propose a model for describing the parallel performance of multigrid software on distributed memory architectures. The goal of the model is to allow reliable predictions to be m...
Giuseppe Romanazzi, Peter K. Jimack
143
Voted
DAC
2006
ACM
16 years 5 months ago
Rapid and low-cost context-switch through embedded processor customization for real-time and control applications
In this paper, we present a methodology for low-cost and rapid context switch for multithreaded embedded processors with realtime guarantees. Context-switch, which involves saving...
Xiangrong Zhou, Peter Petrov
ICS
2009
Tsinghua U.
15 years 11 months ago
High-performance regular expression scanning on the Cell/B.E. processor
Matching regular expressions (regexps) is a very common workload. For example, tokenization, which consists of recognizing words or keywords in a character stream, appears in ever...
Daniele Paolo Scarpazza, Gregory F. Russell