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CAMP
2005
IEEE
15 years 6 months ago
16-bit Floating Point Instructions for Embedded Multimedia Applications
— We have simulated the implementation of 16-bit floating point instructions on a Pentium4 and PowerPC G4 and G5 to evaluate the performance impact of these instructions in embed...
Lionel Lacassagne, Daniel Etiemble, S. A. Ould Kab...
154
Voted
DTJ
1998
171views more  DTJ 1998»
15 years 4 months ago
Measurement and Analysis of C and C++ Performance
ir increasing use of abstraction, modularity, delayed binding, polymorphism, and source reuse, especially when these attributes are used in combination. Modern processor architectu...
Hemant G. Rotithor, Kevin W. Harris, Mark W. Davis
FPL
2004
Springer
106views Hardware» more  FPL 2004»
15 years 10 months ago
FiPRe: An Implementation Model to Enable Self-Reconfigurable Applications
ASIPs and reconfigurable processors are architectural choices to extend the capabilities of a given processor. ASIPs suffer from fixed hardware after design, while ASIPs and reconf...
Leandro Möller, Ney Laert Vilar Calazans, Fer...
130
Voted
CISIS
2010
IEEE
15 years 10 months ago
A Parallel Programming Framework for Multi-core DNA Sequence Alignment
—A new parallel programming framework for DNA sequence alignment in homogeneous multi-core processor architectures is proposed. Contrasting with traditional coarse-grained parall...
Tiago Jose Barreiros Martins de Almeida, Nuno Fili...
SPAA
1992
ACM
15 years 8 months ago
Subset Barrier Synchronization on a Private-Memory Parallel System
A global barrier synchronizes all processors in a parallel system. This paper investigates algorithms that allow disjoint subsets of processors to synchronize independently and in...
Anja Feldmann, Thomas R. Gross, David R. O'Hallaro...