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CHARME
2001
Springer
92views Hardware» more  CHARME 2001»
14 years 2 months ago
Formal Verification of the VAMP Floating Point Unit
We report on the formal verification of the floating point unit used in the VAMP processor. The FPU is fully IEEE compliant, and supports denormals and exceptions in hardware. The ...
Christoph Berg, Christian Jacobi 0002
CODES
2008
IEEE
14 years 22 days ago
Specification-based compaction of directed tests for functional validation of pipelined processors
Functional validation is a major bottleneck in microprocessor design methodology. Simulation is the widely used method for functional validation using billions of random and biase...
Heon-Mo Koo, Prabhat Mishra
DAC
1996
ACM
14 years 3 months ago
Techniques for Verifying Superscalar Microprocessors
Burch and Dill [3] described an automatic method for verifying a pipelined processor against its instruction setarchitecture(ISA). We describethree techniquesfor improving this me...
Jerry R. Burch
DAC
1997
ACM
14 years 2 months ago
Formal Verification of a Superscalar Execution Unit
Abstract. Many modern systems are designed as a set of interconnected reactive subsystems. The subsystem verification task is to verify an implementation of the subsystem against t...
Kyle L. Nelson, Alok Jain, Randal E. Bryant
CAV
2004
Springer
154views Hardware» more  CAV 2004»
14 years 2 months ago
Automatic Verification of Sequential Consistency for Unbounded Addresses and Data Values
Sequential consistency is the archetypal correctness condition for the memory protocols of shared-memory multiprocessors. Typically, such protocols are parameterized by the number ...
Jesse D. Bingham, Anne Condon, Alan J. Hu, Shaz Qa...