43 search results - page 4 / 9 » Processor-time-optimal systolic arrays |
ISCAS
1993
IEEE
13 years 11 months ago
1993
IEEE
We present in this paper systolic arrays with constant number of input/output (I/O) ports for twodimensional (2-D) FIR and IIR filtering. Our design has an array of L × N proces...
ASAP
2006
IEEE
14 years 1 months ago
2006
IEEE
In the simulation of quantum circuits the matrices and vectors used to represent unitary operations and qubit states grow exponentially as the number of qubits increase. For insta...
ARC
2010
Springer
13 years 11 months ago
2010
Springer
Coarse Grained Reconfigurable Array (CGRA) architectures give high throughput and data reuse for regular algorithms while providing flexibility to execute multiple algorithms on th...
IPPS
2003
IEEE
14 years 28 days ago
2003
IEEE
This paper describes a hardware architecture for modular multiplication operation which is efficient for bit-lengths suitable for both commonly used types of Public Key Cryptogra...
FPL
2008
Springer
13 years 9 months ago
2008
Springer
Wavefront algorithms, such as the Smith-Waterman algorithm, are commonly used in bioinformatics for exact local and global sequence alignment. These algorithms are highly computat...