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JUCS
2006
112views more  JUCS 2006»
13 years 9 months ago
A Multi-objective Genetic Approach to Mapping Problem on Network-on-Chip
Abstract: Advances in technology now make it possible to integrate hundreds of cores (e.g. general or special purpose processors, embedded memories, application specific components...
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi
TVLSI
2008
164views more  TVLSI 2008»
13 years 9 months ago
Dynamically Configurable Bus Topologies for High-Performance On-Chip Communication
The on-chip communication architecture is a major determinant of overall performance in complex System-on-Chip (SoC) designs. Since the communication requirements of SoC components...
Krishna Sekar, Kanishka Lahiri, Anand Raghunathan,...
VLSISP
2008
100views more  VLSISP 2008»
13 years 9 months ago
Memory-constrained Block Processing for DSP Software Optimization
Digital signal processing (DSP) applications involve processing long streams of input data. It is important to take into account this form of processing when implementing embedded ...
Ming-Yung Ko, Chung-Ching Shen, Shuvra S. Bhattach...
RSA
2000
170views more  RSA 2000»
13 years 9 months ago
Delayed path coupling and generating random permutations
We analyze various stochastic processes for generating permutations almost uniformly at random in distributed and parallel systems. All our protocols are simple, elegant and are b...
Artur Czumaj, Miroslaw Kutylowski
PE
2010
Springer
102views Optimization» more  PE 2010»
13 years 7 months ago
Extracting state-based performance metrics using asynchronous iterative techniques
Solution of large sparse linear fixed-point problems lies at the heart of many important performance analysis calculations. These calculations include steady-state, transient and...
Douglas V. de Jager, Jeremy T. Bradley
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