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CGO
2004
IEEE
14 years 2 months ago
FLASH: Foresighted Latency-Aware Scheduling Heuristic for Processors with Customized Datapaths
Application-specific instruction set processors (ASIPs) have the potential to meet the challenging cost, performance, and power goals of future embedded processors by customizing ...
Manjunath Kudlur, Kevin Fan, Michael L. Chu, Rajiv...
EUC
2006
Springer
14 years 2 months ago
Dynamic Repartitioning of Real-Time Schedule on a Multicore Processor for Energy Efficiency
Multicore processors promise higher throughput at lower power consumption than single core processors. Thus in the near future they will be widely used in hard real-time systems as...
Euiseong Seo, Yongbon Koo, Joonwon Lee
CISIS
2010
IEEE
14 years 2 months ago
Automatic Offloading of C++ for the Cell BE Processor: A Case Study Using Offload
Offload C++ is an extended version of the C++ language, together with a compiler and runtime system, for automatically offloading general-purpose C++ code to run on the Synergistic...
Alastair F. Donaldson, Uwe Dolinsky, Andrew Richar...
CSREAESA
2009
13 years 12 months ago
Embedded Processor Based Fault Injection and SEU Emulation for FPGAs
Two embedded processor based fault injection case studies are presented which are applicable to Field Programmable Gate Arrays (FPGAs) and FPGA cores in configurable System-on-Chip...
Bradley F. Dutton, Mustafa Ali, Charles E. Stroud,...
IPPS
2010
IEEE
13 years 8 months ago
Processor affinity and MPI performance on SMP-CMP clusters
Clusters of Symmetric MultiProcessing (SMP) nodes with multi-core Chip-Multiprocessors (CMP), also known as SMP-CMP clusters, are becoming ubiquitous today. For Message Passing int...
Chi Zhang, Xin Yuan, Ashok Srinivasan