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PLDI
1995
ACM
13 years 11 months ago
Improving Balanced Scheduling with Compiler Optimizations that Increase Instruction-Level Parallelism
Traditional list schedulers order instructions based on an optimistic estimate of the load latency imposed by the hardware and therefore cannot respond to variations in memory lat...
Jack L. Lo, Susan J. Eggers
ECBS
2010
IEEE
224views Hardware» more  ECBS 2010»
14 years 2 months ago
Timed Automata Model for Component-Based Real-Time Systems
—One of the key challenges in modern real-time embedded systems is safe composition of different software components. Formal verification techniques provide the means for design...
Georgiana Macariu, Vladimir Cretu
WSC
2008
13 years 10 months ago
Economic efficiency analysis of wafer fabrication facilities
Semiconductor industry is capital intensive and competitive, and thus efficiently utilizing resources to provide products and services is essential for maintaining competitive adv...
Wen-Chih Chen, Chen-Fu Chien, Ming-Hsuan Chou
SPLC
2007
13 years 9 months ago
Product Line Implementation using Aspect-Oriented and Model-Driven Software Development
Software product line engineering aims to reduce development time, effort, cost, and complexity by taking advantage of the commonality within a portfolio of similar products. The ...
Markus Völter, Iris Groher
VTC
2010
IEEE
175views Communications» more  VTC 2010»
13 years 6 months ago
Sensitivity Analysis of the Optimal Parameter Settings of an LTE Packet Scheduler
—Advanced packet scheduling schemes in 3G/3G+ mobile networks provide one or more parameters to optimise the trade-off between QoS and resource efficiency. In this paper we stud...
I. Fernandez Diaz, Desislava C. Dimitrova, Kathlee...