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ICS
2009
Tsinghua U.
14 years 1 months ago
A comprehensive power-performance model for NoCs with multi-flit channel buffers
Large Multi-Processor Systems-on-Chip use Networks-on-Chip with a high degree of reusability and scalability for message communication. Therefore, network infrastructure is a cruc...
Mohammad Arjomand, Hamid Sarbazi-Azad
SIGMOD
2008
ACM
190views Database» more  SIGMOD 2008»
14 years 9 months ago
OLTP through the looking glass, and what we found there
Online Transaction Processing (OLTP) databases include a suite of features -- disk-resident B-trees and heap files, locking-based concurrency control, support for multi-threading ...
Stavros Harizopoulos, Daniel J. Abadi, Samuel Madd...
ISCA
2002
IEEE
115views Hardware» more  ISCA 2002»
14 years 1 months ago
SafetyNet: Improving the Availability of Shared Memory Multiprocessors with Global Checkpoint/Recovery
We develop an availability solution, called SafetyNet, that uses a unified, lightweight checkpoint/recovery mechanism to support multiple long-latency fault detection schemes. At...
Daniel J. Sorin, Milo M. K. Martin, Mark D. Hill, ...
HPCA
2009
IEEE
14 years 9 months ago
Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs
Performance and power consumption of an on-chip interconnect that forms the backbone of Chip Multiprocessors (CMPs), are directly influenced by the underlying network topology. Bo...
Reetuparna Das, Soumya Eachempati, Asit K. Mishra,...
BMCBI
2011
13 years 13 days ago
PeakRanger: A cloud-enabled peak caller for ChIP-seq data
Background: Chromatin immunoprecipitation (ChIP), coupled with massively parallel short-read sequencing (seq) is used to probe chromatin dynamics. Although there are many algorith...
Xin Feng, Robert Grossman, Lincoln Stein