10 search results - page 1 / 2 » Program Balance and Its Impact on High Performance RISC Arch... |
HPCA
1995
IEEE
14 years 2 months ago
1995
IEEE
Information on the behavior of programs is essential for deciding the number and nature of functional units in high performance architectures. In this paper, we present studies on...
SBACPAD
2008
IEEE
14 years 5 months ago
2008
IEEE
This work presents an implementation of Neocognitron Neural Network, using a high performance computing architecture based on GPU (Graphics Processing Unit). Neocognitron is an ar...
CLUSTER
2007
IEEE
14 years 5 months ago
2007
IEEE
— The Cell Broadband Engine (BE) is a heterogeneous multicore processor, combining a general-purpose POWER architecture core with eight independent single-instructionmultiple-dat...
IPPS
2007
IEEE
14 years 5 months ago
2007
IEEE
This paper explores generating efficient, portable HighSpeed Producer Consumer (HSPC) code on current shared memory architectures: Chip Multi-Processors (CMP), Simultaneous Multi...
MOBIHOC
2005
ACM
14 years 10 months ago
2005
ACM
We consider a wireless sensor network in which sensors are grouped into clusters, each with its own cluster head (CH). Each CH collects data from sensors in its cluster and relays...