Sciweavers

79 search results - page 11 / 16
» Program Slicing of Hardware Description Languages
Sort
View
DATE
2009
IEEE
136views Hardware» more  DATE 2009»
14 years 2 months ago
A novel approach to entirely integrate Virtual Test into test development flow
– In this paper, we present an open architecture Virtual Test Environment (VTE) which can be easily integrated into various modularized Automatic Test Systems (ATS) compliant to ...
Ping Lu, Daniel Glaser, Gürkan Uygur, Klaus H...
CASES
2001
ACM
13 years 11 months ago
A compiler framework for mapping applications to a coarse-grained reconfigurable computer architecture
The rapid growth of silicon densities has made it feasible to deploy reconfigurable hardware as a highly parallel computing platform. However, in most cases, the application needs...
Girish Venkataramani, Walid A. Najjar, Fadi J. Kur...
FPL
2004
Springer
89views Hardware» more  FPL 2004»
14 years 25 days ago
HW/SW Co-design by Automatic Embedding of Complex IP Cores
Complex SoC and platform-based designs require integration of configurable IP cores from multiple sources. Even automatic compilation flows from a high-level description to HW/SW s...
Holger Lange, Andreas Koch
CAV
2009
Springer
177views Hardware» more  CAV 2009»
14 years 8 months ago
Software Transactional Memory on Relaxed Memory Models
Abstract. Pseudo-code descriptions of STMs assume sequentially consistent program execution and atomicity of high-level STM operations like read, write, and commit. These assumptio...
Rachid Guerraoui, Thomas A. Henzinger, Vasu Singh
MEMOCODE
2007
IEEE
14 years 1 months ago
Scheduling as Rule Composition
Bluespec is a high-level hardware description language used for architectural exploration, hardware modeling and synthesis of semiconductor chips. In Bluespec, one views hardware ...
Nirav Dave, Arvind, Michael Pellauer