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TVLSI
1998
99views more  TVLSI 1998»
13 years 7 months ago
Some experiments about wave pipelining on FPGA's
— Wave pipelining offers a unique combination of high speed, low latency, and moderate power consumption. The construction of wave pipelines is benefited by the use of gates and...
Eduardo I. Boemo, Sergio López-Buedo, Juan ...
FPGA
2001
ACM
152views FPGA» more  FPGA 2001»
13 years 11 months ago
A pipelined architecture for partitioned DWT based lossy image compression using FPGA's
Discrete wavelet transformations (DWT) followed by embedded zerotree encoding is a very efficient technique for image compression [2, 5, 4]. However, the algorithms proposed in l...
Jörg Ritter, Paul Molitor
ISVLSI
2005
IEEE
169views VLSI» more  ISVLSI 2005»
14 years 28 days ago
High Performance Array Processor for Video Decoding
high NRE cost. Therefore, general purpose programmable processors using software to perform various functions become more attractive since programmability can simplify system devel...
J. Lee, Narayanan Vijaykrishnan, Mary Jane Irwin
IPPS
2005
IEEE
14 years 28 days ago
Building on a Framework: Using FG for More Flexibility and Improved Performance in Parallel Programs
We describe new features of FG that are designed to improve performance and extend the range of computations that fit into its framework. FG (short for Framework Generator) is a ...
Elena Riccio Davidson, Thomas H. Cormen
FPGA
1997
ACM
124views FPGA» more  FPGA 1997»
13 years 11 months ago
YARDS: FPGA/MPU Hybrid Architecture for Telecommunication Data Processing
This paper presents a novel system architecture applicable to high-performance and flexible transport data processing which includes complex protocol operation and a network contr...
Akihiro Tsutsui, Toshiaki Miyazaki