44 search results - page 7 / 9 » Programmable Hardware Implementation for the Median-Rational... |
154
click to vote
RTSS
2006
IEEE
15 years 9 months ago
2006
IEEE
Modern FPGA devices, which include (multiple) processor core(s) as diffused IP on the silicon die, provide an excellent platform for developing custom multiprocessor systems-on-pr...
108
Voted
COMPCON
1995
IEEE
15 years 7 months ago
1995
IEEE
This paper describes Tempest, a collection of mechanisms for communication and synchronization in parallel programs. With these mechanisms, authors of compilers, libraries, and ap...
183
Voted
ERSA
2007
15 years 4 months ago
2007
Abstract: If the computational demands of an interactive graphics rendering application cannot be met by a single commodity Graphics Processing Unit (GPU), multiple graphics accele...
145
Voted
SC
2000
ACM
15 years 7 months ago
2000
ACM
The current trend in HPC hardware is towards clusters of shared-memory (SMP) compute nodes. For applications developers the major question is how best to program these SMP cluster...
138
Voted
EUROPAR
2008
Springer
15 years 5 months ago
2008
Springer
Over the last decade, Message Passing Interface (MPI) has become a very successful parallel programming environment for distributed memory architectures such as clusters. However, ...