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AIPR
2008
IEEE
13 years 9 months ago
Low-cost, high-speed computer vision using NVIDIA's CUDA architecture
In this paper, we introduce real time image processing techniques using modern programmable Graphic Processing Units (GPU). GPUs are SIMD (Single Instruction, Multiple Data) device...
Seung In Park, Sean P. Ponce, Jing Huang, Yong Cao...
3DPVT
2006
IEEE
233views Visualization» more  3DPVT 2006»
14 years 1 months ago
Scanline Optimization for Stereo on Graphics Hardware
In this work we propose a scanline optimization procedure for computational stereo using a linear smoothness cost model performed by programmable graphics hardware. The main idea ...
Christopher Zach, Mario Sormann, Konrad F. Karner
FPGA
1997
ACM
124views FPGA» more  FPGA 1997»
13 years 11 months ago
YARDS: FPGA/MPU Hybrid Architecture for Telecommunication Data Processing
This paper presents a novel system architecture applicable to high-performance and flexible transport data processing which includes complex protocol operation and a network contr...
Akihiro Tsutsui, Toshiaki Miyazaki
ASPDAC
2001
ACM
100views Hardware» more  ASPDAC 2001»
13 years 11 months ago
Low power implementation of a turbo-decoder on programmable architectures
Low Power is an extremely important issue for future mobile radio systems. Channel decoders are essential building blocks of base-band signal processing units in mobile terminal ar...
Frank Gilbert, Alexander Worm, Norbert Wehn
UIST
2004
ACM
14 years 25 days ago
Revisiting visual interface programming: creating GUI tools for designers and programmers
Involving graphic designers in the large-scale development of user interfaces requires tools that provide more graphical flexibility and support efficient software processes. Th...
Stéphane Chatty, Stéphane Sire, Jean...