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WCET
2010
15 years 12 days ago
Precomputing Memory Locations for Parametric Allocations
Current worst-case execution time (WCET) analyses do not support programs using dynamic memory allocation. This is mainly due to the unpredictability of cache performance introduc...
Jörg Herter, Sebastian Altmeyer
ISCA
2012
IEEE
333views Hardware» more  ISCA 2012»
13 years 5 months ago
Reducing memory reference energy with opportunistic virtual caching
Most modern cores perform a highly-associative translation look aside buffer (TLB) lookup on every memory access. These designs often hide the TLB lookup latency by overlapping it...
Arkaprava Basu, Mark D. Hill, Michael M. Swift
130
Voted
CLUSTER
2009
IEEE
15 years 9 months ago
Integrating software distributed shared memory and message passing programming
Abstract—Software Distributed Shared Memory (SDSM) systems provide programmers with a shared memory programming environment across distributed memory architectures. In contrast t...
H'sien J. Wong, Alistair P. Rendell
ISCA
2008
IEEE
143views Hardware» more  ISCA 2008»
15 years 2 months ago
TokenTM: Efficient Execution of Large Transactions with Hardware Transactional Memory
Current hardware transactional memory systems seek to simplify parallel programming, but assume that large transactions are rare, so it is acceptable to penalize their performance...
Jayaram Bobba, Neelam Goyal, Mark D. Hill, Michael...
120
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IPPS
2010
IEEE
15 years 14 days ago
A PRAM-NUMA model of computation for addressing low-TLP workloads
It is possible to implement the parallel random access machine (PRAM) on a chip multiprocessor (CMP) efficiently with an emulated shared memory (ESM) architecture to gain easy par...
Martti Forsell