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FPL
2006
Springer
242views Hardware» more  FPL 2006»
13 years 11 months ago
TMD-MPI: An MPI Implementation for Multiple Processors Across Multiple FPGAs
With current FPGAs, designers can now instantiate several embedded processors, memory units, and a wide variety of IP blocks to build a single-chip, high-performance multiprocesso...
Manuel Saldaña, Paul Chow
IAJIT
2010
150views more  IAJIT 2010»
13 years 6 months ago
Optimal DSP Based Integer Motion Estimation Implementation for H.264/AVC Baseline Encoder
: The coding gain of the H.264/AVC video encoder mainly comes from the new incorporated prediction tools. However, their enormous computation and ultrahigh memory bandwidth are the...
Imen Werda, Haithem Chaouch, Amine Samet, Mohamed ...
ISCA
1998
IEEE
114views Hardware» more  ISCA 1998»
13 years 11 months ago
The MIT Alewife Machine: Architecture and Performance
Alewife is a multiprocessor architecture that supports up to 512 processing nodes connected over a scalable and cost-effective mesh network at a constant cost per node. The MIT Al...
Anant Agarwal, Ricardo Bianchini, David Chaiken, K...
ICDCS
1991
IEEE
13 years 11 months ago
Supporting the development of network programs
of ‘‘network computers’’ is inherently lessAbstract predictable than that of more traditional distributed memory systems, such as hypercubes [22], since both theFor computa...
Bernd Bruegge, Peter Steenkiste
CCGRID
2006
IEEE
14 years 1 months ago
VODCA: View-Oriented, Distributed, Cluster-Based Approach to Parallel Computing
This paper presents a high-performance Distributed Shared Memory system called VODCA, which supports a novel View-Oriented Parallel Programming on cluster computers. One advantage...
Zhiyi Huang, Wenguang Chen, Martin K. Purvis, Weim...