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SIAMCOMP
2000
79views more  SIAMCOMP 2000»
13 years 7 months ago
Optimal Worst Case Formulas Comparing Cache Memory Associativity
ct Consider an arbitrary program P which is to be executed on a computer with two alternative cache memories. The rst cache has k sets and u blocks in each set, this is denoted a ...
Håkan Lennerstad, Lars Lundberg
ASPLOS
1991
ACM
13 years 11 months ago
Performance Evaluation of Memory Consistency Models for Shared Memory Multiprocessors
The memory consistency model supported by a multiprocessor architecture determines the amount of buffering and pipelining that may be used to hide or reduce the latency of memory ...
Kourosh Gharachorloo, Anoop Gupta, John L. Henness...
TC
1998
13 years 7 months ago
Performance Evaluation and Cost Analysis of Cache Protocol Extensions for Shared-Memory Multiprocessors
—We evaluate three extensions to directory-based cache coherence protocols in shared-memory multiprocessors. These extensions are aimed at reducing the penalties associated with ...
Fredrik Dahlgren, Michel Dubois, Per Stenströ...
FPGA
2001
ACM
139views FPGA» more  FPGA 2001»
13 years 12 months ago
A memory coherence technique for online transient error recovery of FPGA configurations
The partial reconfiguration feature of some of the currentgeneration Field Programmable Gate Arrays (FPGAs) can improve dependability by detecting and correcting errors in onchip ...
Wei-Je Huang, Edward J. McCluskey
VLSISP
2008
106views more  VLSISP 2008»
13 years 7 months ago
Architecture Considerations for Multi-Format Programmable Video Processors
Many different video processor architectures exist. Its architecture gives a processor strength for a particular application. Hardwired logic yields the best performance/cost, but ...
Jonah Probell