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ISCA
2006
IEEE
144views Hardware» more  ISCA 2006»
15 years 2 months ago
Conditional Memory Ordering
Conventional relaxed memory ordering techniques follow a proactive model: at a synchronization point, a processor makes its own updates to memory available to other processors by ...
Christoph von Praun, Harold W. Cain, Jong-Deok Cho...
PASTE
2010
ACM
15 years 4 months ago
Null dereference analysis in practice
Many analysis techniques have been proposed to determine when a potentially null value may be dereferenced. But we have observed in practice that not every potential null derefere...
Nathaniel Ayewah, William Pugh
IJDE
2007
123views more  IJDE 2007»
15 years 2 months ago
Identifying Authorship by Byte-Level N-Grams: The Source Code Author Profile (SCAP) Method
Source code author identification deals with identifying the most likely author of a computer program, given a set of predefined author candidates. There are several scenarios whe...
Georgia Frantzeskou, Efstathios Stamatatos, Stefan...

Lecture Notes
1005views
17 years 2 months ago
Lectures on reconfigurable computing
Driven by recent innovations in Field-Programmable Gate Arrays (FPGAs), reconfigurable computing offers unique ways to accelerate key algorithms. FPGAs offer a programmable logic f...
Sherief Reda
CP
2007
Springer
15 years 8 months ago
Scheduling Conditional Task Graphs
The increasing levels of system integration in Multi-Processor System-on-Chips (MPSoCs) emphasize the need for new design flows for efficient mapping of multi-task applications o...
Michele Lombardi, Michela Milano
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