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DAC
2002
ACM
14 years 10 months ago
Dynamic hardware plugins in an FPGA with partial run-time reconfiguration
Tools and a design methodology have been developed to support partial run-time reconfiguration of FPGA logic on the Field Programmable Port Extender. High-speed Internet packet pr...
Edson L. Horta, John W. Lockwood, David E. Taylor,...
SIGSOFT
2007
ACM
14 years 10 months ago
Mining API patterns as partial orders from source code: from usage scenarios to specifications
A software system interacts with third-party libraries through various APIs. Using these library APIs often needs to follow certain usage patterns. Furthermore, ordering rules (sp...
Mithun Acharya, Tao Xie, Jian Pei, Jun Xu
CCS
2009
ACM
14 years 4 months ago
A practical property-based bootstrap architecture
Binary attestation, as proposed by the Trusted Computing Group (TCG), is a pragmatic approach for software integrity protection and verification. However, it has also various sho...
René Korthaus, Ahmad-Reza Sadeghi, Christia...
ICS
2009
Tsinghua U.
14 years 4 months ago
Combining thread level speculation helper threads and runahead execution
With the current trend toward multicore architectures, improved execution performance can no longer be obtained via traditional single-thread instruction level parallelism (ILP), ...
Polychronis Xekalakis, Nikolas Ioannou, Marcelo Ci...
CASES
2009
ACM
14 years 4 months ago
CheckerCore: enhancing an FPGA soft core to capture worst-case execution times
Embedded processors have become increasingly complex, resulting in variable execution behavior and reduced timing predictability. On such processors, safe timing specifications e...
Jin Ouyang, Raghuveer Raghavendra, Sibin Mohan, Ta...
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