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LCTRTS
2007
Springer
14 years 4 months ago
Addressing instruction fetch bottlenecks by using an instruction register file
The Instruction Register File (IRF) is an architectural extension for providing improved access to frequently occurring instructions. An optimizing compiler can exploit an IRF by ...
Stephen Roderick Hines, Gary S. Tyson, David B. Wh...
SEMWEB
2007
Springer
14 years 4 months ago
Extending Fuzzy Description Logics with a Possibilistic Layer
Classical ontologies are not suitable to represent imprecise nor uncertain pieces of information. As a solution we will combine fuzzy Description Logics with a possibilistic layer....
Fernando Bobillo, Miguel Delgado, Juan Góme...
VEE
2006
ACM
142views Virtualization» more  VEE 2006»
14 years 4 months ago
Secure and practical defense against code-injection attacks using software dynamic translation
One of the most common forms of security attacks involves exploiting a vulnerability to inject malicious code into an executing application and then cause the injected code to be ...
Wei Hu, Jason Hiser, Daniel Williams, Adrian Filip...
ACMMSP
2005
ACM
101views Hardware» more  ACMMSP 2005»
14 years 3 months ago
Transparent pointer compression for linked data structures
64-bit address spaces are increasingly important for modern applications, but they come at a price: pointers use twice as much memory, reducing the effective cache capacity and m...
Chris Lattner, Vikram S. Adve
FPL
2005
Springer
122views Hardware» more  FPL 2005»
14 years 3 months ago
FPGA-Aware Garbage Collection in Java
— During codesign of a system, one still runs into the impedance mismatch between the software and hardware worlds. er identifies the different levels of abstraction of hardware...
Philippe Faes, Mark Christiaens, Dries Buytaert, D...
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