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DATE
2009
IEEE
90views Hardware» more  DATE 2009»
14 years 3 months ago
Property analysis and design understanding
—Verification is a major issue in circuit and system design. Formal methods like bounded model checking (BMC) can guarantee a high quality of the verification. There are severa...
Ulrich Kühne, Daniel Große, Rolf Drechs...
QEST
2008
IEEE
14 years 3 months ago
Quantitative Model-Checking of One-Clock Timed Automata under Probabilistic Semantics
In [3] a probabilistic semantics for timed automata has been defined in order to rule out unlikely (sequences of) events. The qualitative model-checking problem for LTL propertie...
Nathalie Bertrand, Patricia Bouyer, Thomas Brihaye...
SAT
2009
Springer
153views Hardware» more  SAT 2009»
14 years 3 months ago
Does Advice Help to Prove Propositional Tautologies?
One of the starting points of propositional proof complexity is the seminal paper by Cook and Reckhow [6], where they defined propositional proof systems as poly-time computable f...
Olaf Beyersdorff, Sebastian Müller
TII
2008
98views more  TII 2008»
13 years 8 months ago
Formal Methods for Systems Engineering Behavior Models
Abstract--Safety analysis in Systems Engineering (SE) processes, as usually implemented, rarely relies on formal methods such as model checking since such techniques, however power...
Charlotte Seidner, Olivier H. Roux
ECAI
2010
Springer
13 years 9 months ago
On the Verification of Very Expressive Temporal Properties of Non-terminating Golog Programs
Abstract. The agent programming language GOLOG and the underlying Situation Calculus have become popular means for the modelling and control of autonomous agents such as mobile rob...
Jens Claßen, Gerhard Lakemeyer