798 search results - page 48 / 160 » Proving More Properties with Bounded Model Checking |
PLDI
2000
ACM
14 years 1 months ago
2000
ACM
We show how to determine statically whether it is safe for untrusted machine code to be loaded into a trusted host system. Our safety-checking technique operates directly on the u...
VLSID
2010
IEEE
13 years 6 months ago
2010
IEEE
Directed test generation is important for the functional verification of complex system-on-chip designs. SAT based bounded model checking is promising for counterexample generatio...
DLT
2007
13 years 10 months ago
2007
Visibly Pushdown Automata (VPA) are a special case of pushdown machines where the stack operations are driven by the input. In this paper, we consider VPA with two stacks, namely 2...
ETFA
2006
IEEE
14 years 2 months ago
2006
IEEE
This paper presents a new approach to modelling and verification of function block applications of the IEC 61499 standard. The approach uses the language of logic programming Prol...
FMCAD
2004
Springer
14 years 15 days ago
2004
Springer
In this paper we demonstrate a potential extension of formal verification methodology in order to deal with time-domain properties of analog and mixed-signal circuits whose dynamic...