Sciweavers

2555 search results - page 489 / 511
» Quantifiers and Working Memory
Sort
View
PEPM
1999
ACM
13 years 11 months ago
Certifying Compilation and Run-Time Code Generation
A certifying compiler takes a source language program and produces object code, as well as a certi cate" that can be used to verify that the object code satis es desirable pr...
Luke Hornof, Trevor Jim
CAV
1998
Springer
175views Hardware» more  CAV 1998»
13 years 11 months ago
An ACL2 Proof of Write Invalidate Cache Coherence
As a pedagogical exercise in ACL2, we formalize and prove the correctness of a write invalidate cache scheme. In our formalization, an arbitrary number of processors, each with its...
J. Strother Moore
FCCM
1997
IEEE
103views VLSI» more  FCCM 1997»
13 years 11 months ago
An FPGA architecture for DRAM-based systolic computations
We propose an FPGA chip architecture based on a conventional FPGA logic array core, in which I/O pins are clocked at a much higher rate than that of the logic array that they serv...
Norman Margolus
TACAS
1998
Springer
81views Algorithms» more  TACAS 1998»
13 years 11 months ago
Formal Design and Analysis of a Gear Controller
In this paper, we report on an application of the validation and veri cation tool kit Uppaal in the design and analysis of a prototype gear controller, carried out in a joint proje...
Magnus Lindahl, Paul Pettersson, Wang Yi
VLDB
1998
ACM
147views Database» more  VLDB 1998»
13 years 11 months ago
Architecture of Oracle Parallel Server
Oracle Parallel Server (OPS) is a shared disk RDBMS. We present a high level overview of the main architectural issues of OPS and their evolution throughout the releases of the Or...
Roger Bamford, D. Butler, Boris Klots, N. MacNaugh...