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IPPS
2006
IEEE
14 years 5 months ago
Design flow for optimizing performance in processor systems with on-chip coarse-grain reconfigurable logic
A design flow for processor platforms with on-chip coarse-grain reconfigurable logic is presented. The reconfigurable logic is realized by a 2-Dimensional Array of Processing Elem...
Michalis D. Galanis, Grigoris Dimitroulakos, Const...
MICRO
2003
IEEE
148views Hardware» more  MICRO 2003»
14 years 4 months ago
Fast Secure Processor for Inhibiting Software Piracy and Tampering
Due to the widespread software piracy and virus attacks, significant efforts have been made to improve security for computer systems. For stand-alone computers, a key observation...
Jun Yang 0002, Youtao Zhang, Lan Gao
NDSS
2008
IEEE
14 years 5 months ago
Analyzing Privacy in Enterprise Packet Trace Anonymization
Accurate network measurement through trace collection is critical for advancing network design and for maintaining secure, reliable networks. Unfortunately, the release of network...
Bruno F. Ribeiro, Weifeng Chen, Gerome Miklau, Don...
INFOCOM
2005
IEEE
14 years 4 months ago
Hybrid search schemes for unstructured peer-to-peer networks
— We study hybrid search schemes for unstructured peer-to-peer networks. We quantify performance in terms of number of hits, network overhead, and response time. Our schemes comb...
Christos Gkantsidis, Milena Mihail, Amin Saberi
ERCIMDL
1998
Springer
133views Education» more  ERCIMDL 1998»
14 years 3 months ago
MarketNet: Using Virtual Currency to Protect Information Systems
This paper describes novel market-based technologies for systematic, quantifiable and predictable protection of information systems against attacks. These technologies, incorporate...
Yechiam Yemini, Apostolos Dailianas, Danilo Floris...