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HPCA
2009
IEEE
14 years 9 months ago
PageNUCA: Selected policies for page-grain locality management in large shared chip-multiprocessor caches
As the last-level on-chip caches in chip-multiprocessors increase in size, the physical locality of on-chip data becomes important for delivering high performance. The non-uniform...
Mainak Chaudhuri
IPPS
2006
IEEE
14 years 2 months ago
A segment-based DSM supporting large shared object space
This paper introduces a software DSM that can extend its shared object space exceeding 4GB in a 32bit commodity cluster environment. This is achieved through the dynamic memory ma...
Benny Wang-Leung Cheung, Cho-Li Wang
ISCA
2007
IEEE
174views Hardware» more  ISCA 2007»
14 years 2 months ago
An integrated hardware-software approach to flexible transactional memory
There has been considerable recent interest in the support of transactional memory (TM) in both hardware and software. We present an intermediate approach, in which hardware is us...
Arrvindh Shriraman, Michael F. Spear, Hemayet Hoss...
SPDP
1993
IEEE
14 years 16 days ago
Fast Rehashing in PRAM Emulations
In PRAM emulations, universal hashing is a well-known method for distributing the address space among memory modules. However, if the memory access patterns of an application ofte...
J. Keller
ARCS
2009
Springer
14 years 3 months ago
Improving Memory Subsystem Performance Using ViVA: Virtual Vector Architecture
The disparity between microprocessor clock frequencies and memory latency is a primary reason why many demanding applications run well below peak achievable performance. Software c...
Joseph Gebis, Leonid Oliker, John Shalf, Samuel Wi...