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JPDC
2006
111views more  JPDC 2006»
13 years 7 months ago
Designing irregular parallel algorithms with mutual exclusion and lock-free protocols
Irregular parallel algorithms pose a significant challenge for achieving high performance because of the difficulty predicting memory access patterns or execution paths. Within an...
Guojing Cong, David A. Bader
IJHPCN
2006
106views more  IJHPCN 2006»
13 years 7 months ago
Performance evaluation of the Sun Fire Link SMP clusters
As symmetric multiprocessors become commonplace, the interconnection networks and the communication system software in clusters of multiprocessors become critical to achieving high...
Ying Qian, Ahmad Afsahi, Nathan R. Fredrickson, Re...
CODES
2009
IEEE
14 years 2 months ago
An on-chip interconnect and protocol stack for multiple communication paradigms and programming models
A growing number of applications, with diverse requirements, are integrated on the same System on Chip (SoC) in the form of hardware and software Intellectual Property (IP). The d...
Andreas Hansson, Kees Goossens
APPINF
2003
13 years 8 months ago
A Multithreaded Compiler Backend for High-level Array Programming
Whenever large homogeneous data structures need to be processed in a non-trivial way, e.g. in computational sciences, image processing, or system simulation, high-level array prog...
Clemens Grelck
ISCA
2012
IEEE
243views Hardware» more  ISCA 2012»
11 years 10 months ago
BlockChop: Dynamic squash elimination for hybrid processor architecture
Hybrid processors are HW/SW co-designed processors that leverage blocked-execution, the execution of regions of instructions as atomic blocks, to facilitate aggressive speculative...
Jason Mars, Naveen Kumar