214 search results - page 18 / 43 » Quasi-Resonant Interconnects: A Low Power Design Methodology |
IEEEPACT
2002
IEEE
14 years 25 days ago
2002
IEEE
Clustering is an effective microarchitectural technique for reducing the impact of wire delays, the complexity, and the power requirements of microprocessors. In this work, we inv...
NOCS
2010
IEEE
13 years 5 months ago
2010
IEEE
The number of cores present on-chip is increasing rapidly. The on-chip network that connects these cores needs to scale efficiently. The topology of on-chip networks is an importan...
DAC
2007
ACM
14 years 9 months ago
2007
ACM
We propose a design and optimization methodology for high performance and ultra low power digital applications on flexible substrate using Low Temperature Polycrystalline Silicon ...
JEC
2006
13 years 7 months ago
2006
We present an overview of the Synchroscalar single-chip, multi-core processor. Through the design of Synchroscalar, we find that high energy efficiency and low complexity can be a...
TWC
2008
13 years 7 months ago
2008
Abstract-- In many portable devices, wireless network interfaces consume upwards of 30% of scarce system energy. Reducing the transceiver's power consumption to extend the sys...