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» Quasi-Resonant Interconnects: A Low Power Design Methodology
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ICCD
2004
IEEE
103views Hardware» more  ICCD 2004»
14 years 4 months ago
Design-Space Exploration of Power-Aware On/Off Interconnection Networks
— With power a major limiting factor in the design of scalable interconnected systems, power-aware networks will become inherent components of single-chip and multi-chip systems....
Vassos Soteriou, Li-Shiuan Peh
ASPDAC
2012
ACM
265views Hardware» more  ASPDAC 2012»
12 years 3 months ago
GLOW: A global router for low-power thermal-reliable interconnect synthesis using photonic wavelength multiplexing
In this paper, we examine the integration potential and explore the design space of low power thermal reliable on-chip interconnect synthesis featuring nanophotonics Wavelength Di...
Duo Ding, Bei Yu, David Z. Pan
SBCCI
2003
ACM
160views VLSI» more  SBCCI 2003»
14 years 1 months ago
Novel Design Methodology for High-Performance XOR-XNOR Circuit Design
As we scale down to deep submicron (DSM) technology, noise is becoming a metric of equal importance as power, speed, and area. Smaller feature sizes, low voltage, and high frequen...
Sumeer Goel, Mohamed A. Elgamel, Magdy A. Bayoumi
ICCAD
2007
IEEE
119views Hardware» more  ICCAD 2007»
13 years 9 months ago
IntSim: A CAD tool for optimization of multilevel interconnect networks
– Interconnect issues are becoming increasingly important for ULSI systems. IntSim, an interconnect CAD tool, has been developed to obtain pitches of different wiring levels and ...
Deepak C. Sekar, Azad Naeemi, Reza Sarvari, Jeffre...
DAC
2001
ACM
14 years 8 months ago
A2BC: Adaptive Address Bus Coding for Low Power Deep Sub-Micron Designs
Due to larger buses (length, width) and deep sub-micron effects where coupling capacitances between bus lines are in the same order of magnitude as base capacitances, power consum...
Haris Lekatsas, Jörg Henkel