Sciweavers

149 search results - page 9 / 30
» QuickSpec: Guessing Formal Specifications Using Testing
Sort
View
ENTCS
2008
106views more  ENTCS 2008»
13 years 7 months ago
Verifying Test-Hypotheses: An Experiment in Test and Proof
HOL-TestGen is a specification and test case generation environment extending the interactive theorem prover Isabelle/HOL. The HOL-TestGen method is two-staged: first, the origina...
Achim D. Brucker, Lukas Brügger, Burkhart Wol...
PTS
2000
99views Hardware» more  PTS 2000»
13 years 8 months ago
Verification of Test Suites
We present a formal approach to check the correctness and to propose corrections of hand-written test suites with respect to a formal specification of the protocol implementations ...
Claude Jard, Thierry Jéron, Pierre Morel
UML
2004
Springer
14 years 25 days ago
System-on-Chip Verification Process Using UML
Abstract. In this paper, we propose a verification methodology for System-OnChip (SoC) design using Unified Modeling Language (UML). We introduce UML as a formal model to analyze a...
Qiang Zhu, Tsuneo Nakata, Masataka Mine, Kenichiro...
WOODPECKER
2001
13 years 8 months ago
Consistency Checking of RM-ODP Specifications
Ensuring that specifications are consistent is an important part of specification development and testing. In this paper we introduce the ConsVISor tool for consistency checking o...
Kenneth Baclawski, Mieczyslaw M. Kokar, Jeffrey E....
CHARME
2003
Springer
97views Hardware» more  CHARME 2003»
13 years 11 months ago
Coverage Metrics for Formal Verification
In formal verification, we verify that a system is correct with respect to a specification. Even when the system is proven to be correct, there is still a question of how complete ...
Hana Chockler, Orna Kupferman, Moshe Y. Vardi