5762 search results - page 17 / 1153 » R-tree: A Hardware Implementation |
ISCA
1994
IEEE
14 years 17 days ago
1994
IEEE
We comparethe performance of software-supported shared memory on a general-purpose network to hardware-supported shared memory on a dedicated interconnect. Up to eight processors,...
EUROMICRO
2002
IEEE
14 years 1 months ago
2002
IEEE
In this paper, we propose a new hardware unit that performs a 16 × 1 SAD operation. The hardware unit is intended to augment a general-purpose core. Further, we show that the 16 ...
APCCAS
2006
IEEE
14 years 2 months ago
2006
IEEE
— DAB is a growing communication technology for digital audio broadcasting and demands higher concentration on flexible and cost optimum implementations for use in new mobile ele...
FCCM
2000
IEEE
14 years 26 days ago
2000
IEEE
This paper describes a networked FPGA-based implementation of the FAST (Flexible Adaptable-Size Topology) architecture, a Arti cial Neural Network (ANN) that dynamically adapts it...
FCCM
2005
IEEE
14 years 2 months ago
2005
IEEE
The CLA-EC is a model obtained by combining the concepts of cellular learning automata and evolutionary algorithms. The parallel structure of the CLA-EC makes it suitable for hard...