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JCP
2008
119views more  JCP 2008»
13 years 8 months ago
Performance Comparisons, Design, and Implementation of RC5 Symmetric Encryption Core using Reconfigurable Hardware
With the wireless communications coming to homes and offices, the need to have secure data transmission is of utmost importance. Today, it is important that information is sent con...
Omar S. Elkeelany, Adegoke Olabisi
SC
2009
ACM
14 years 3 months ago
Implementing a high-volume, low-latency market data processing system on commodity hardware using IBM middleware
A stock market data processing system that can handle high data volumes at low latencies is critical to market makers. Such systems play a critical role in algorithmic trading, ri...
Xiaolan J. Zhang, Henrique Andrade, Bugra Gedik, R...
FPGA
2003
ACM
161views FPGA» more  FPGA 2003»
14 years 1 months ago
Implementation of BEE: a real-time large-scale hardware emulation engine
This paper describes the hardware implementation of a real-time, large-scale, multi-chip FPGA (Field Programmable Gate Array) based emulation engine with a capacity of 10 million ...
Chen Chang, Kimmo Kuusilinna, Brian C. Richards, R...
ISCAS
2005
IEEE
101views Hardware» more  ISCAS 2005»
14 years 2 months ago
Parallel algorithm for hardware implementation of inverse halftoning
— A Parallel algorithm and its hardware implementation of Inverse Halftone operation is proposed in this paper. The algorithm is based on Lookup Tables from which the inverse hal...
Umair F. Siddiqi, Sadiq M. Sait, Aamir A. Farooqui
IJON
2007
80views more  IJON 2007»
13 years 8 months ago
Hardware implementation of a novel genetic algorithm
—This paper presents a novel genetic algorithm, termed the Optimum Individual Monogenetic Algorithm (OIMGA) and describes its hardware implementation. As the monogenetic strategy...
Z. Zhu, D. J. Mulvaney, Vassilios A. Chouliaras