Sciweavers

5762 search results - page 36 / 1153
» R-tree: A Hardware Implementation
Sort
View
ET
2008
92views more  ET 2008»
13 years 8 months ago
Hardware and Software Transparency in the Protection of Programs Against SEUs and SETs
Processor cores embedded in systems-on-a-chip (SoCs) are often deployed in critical computations, and when affected by faults they may produce dramatic effects. When hardware harde...
Eduardo Luis Rhod, Carlos Arthur Lang Lisbôa...
ERSA
2010
115views Hardware» more  ERSA 2010»
13 years 6 months ago
Towards Adaptive Networking for Embedded Devices based on Reconfigurable Hardware
Research in communication networks has shown that the Internet architecture is not sufficient for modern communication areas such as the interconnection networks of super computing...
Enno Lübbers, Marco Platzner, Christian Pless...
ASPLOS
2011
ACM
13 years 3 days ago
Hybrid NOrec: a case study in the effectiveness of best effort hardware transactional memory
Transactional memory (TM) is a promising synchronization mechanism for the next generation of multicore processors. Best-effort Hardware Transactional Memory (HTM) designs, such a...
Luke Dalessandro, François Carouge, Sean Wh...
FCCM
2011
IEEE
311views VLSI» more  FCCM 2011»
13 years 7 days ago
String Matching in Hardware Using the FM-Index
—String matching is a ubiquitous problem that arises in a wide range of applications in computing, e.g., packet routing, intrusion detection, web querying, and genome analysis. D...
Edward Fernandez, Walid Najjar, Stefano Lonardi
ISCA
2012
IEEE
248views Hardware» more  ISCA 2012»
11 years 11 months ago
Watchdog: Hardware for safe and secure manual memory management and full memory safety
Languages such as C and C++ use unsafe manual memory management, allowing simple bugs (i.e., accesses to an object after deallocation) to become the root cause of exploitable secu...
Santosh Nagarakatte, Milo M. K. Martin, Steve Zdan...