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130
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PAIRING
2010
Springer
153views Cryptology» more  PAIRING 2010»
15 years 2 months ago
Compact Hardware for Computing the Tate Pairing over 128-Bit-Security Supersingular Curves
This paper presents a novel method for designing compact yet efficient hardware implementations of the Tate pairing over supersingular curves in small characteristic. Since such cu...
Nicolas Estibals
ICASSP
2011
IEEE
14 years 7 months ago
Hardware acceleration of iterative image reconstruction for X-ray computed tomography
X-ray computed tomography (CT) images could be improved using iterative image reconstruction if the 3D conebeam forward- and back-projection computations can be accelerated signif...
Jung Kuk Kim, Zhengya Zhang, Jeffrey A. Fessler
SI3D
2012
ACM
13 years 11 months ago
Decoupled deferred shading for hardware rasterization
In this paper we present decoupled deferred shading: a rendering technique based on a new data structure called compact geometry buffer, which stores shading samples independently...
Gabor Liktor, Carsten Dachsbacher
179
Voted
CVIU
2010
267views more  CVIU 2010»
15 years 1 months ago
Accelerated hardware video object segmentation: From foreground detection to connected components labelling
This paper demonstrates the use of a single-chip FPGA for the segmentation of moving objects in a video sequence. The system maintains highly accurate background models, and integ...
Kofi Appiah, Andrew Hunter, Patrick Dickinson, Hon...
IPPS
2010
IEEE
15 years 1 months ago
Efficient hardware support for the Partitioned Global Address Space
We present a novel architecture of a communication engine for non-coherent distributed shared memory systems. The shared memory is composed by a set of nodes exporting their memory...
Holger Fröning, Heiner Litz