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IPCCC
2006
IEEE
14 years 1 months ago
OS-aware tuning: improving instruction cache energy efficiency on system workloads
Low power has been considered as an important issue in instruction cache (I-cache) designs. Several studies have shown that the I-cache can be tuned to reduce power. These techniq...
Tao Li, Lizy K. John
ASAP
2004
IEEE
127views Hardware» more  ASAP 2004»
13 years 11 months ago
A Public-Key Cryptographic Processor for RSA and ECC
We describe a general-purpose processor architecture for accelerating public-key computations on server systems that demand high performance and flexibility to accommodate large n...
Hans Eberle, Nils Gura, Sheueling Chang Shantz, Vi...
CASES
2006
ACM
14 years 1 months ago
Code transformation strategies for extensible embedded processors
Embedded application requirements, including high performance, low power consumption and fast time to market, are uncommon in the broader domain of general purpose applications. I...
Paolo Bonzini, Laura Pozzi
BIRTHDAY
2006
Springer
13 years 11 months ago
Realistic Worst-Case Execution Time Analysis in the Context of Pervasive System Verification
We describe a gate level design of a FlexRay-like bus interface. An electronic control unit (ECU) is obtained by integrating this interface into the design of the verified VAMP pro...
Steffen Knapp, Wolfgang J. Paul
ISCA
1998
IEEE
119views Hardware» more  ISCA 1998»
13 years 12 months ago
Execution Characteristics of Desktop Applications on Windows NT
This paper examines the performance of desktop applications running on the Microsoft Windows NT operating system on Intel x86 processors, and contrasts these applications to the p...
Dennis C. Lee, Patrick Crowley, Jean-Loup Baer, Th...