Sciweavers

211 search results - page 8 / 43
» REDEFIS: a system with a redefinable instruction set process...
Sort
View
RSP
2000
IEEE
105views Control Systems» more  RSP 2000»
13 years 12 months ago
Processor Models for Retargetable Tools
This paper describes a methodology for developing processor specific tools such as assemblers, disassemblers, processor simulators, compilers etc., using processor models in a ge...
Rajat Moona
LCPC
2000
Springer
13 years 11 months ago
Improving Offset Assignment for Embedded Processors
Embedded systems consisting of the application program ROM, RAM, the embedded processor core, and any custom hardware on a single wafer are becoming increasingly common in applicat...
Sunil Atri, J. Ramanujam, Mahmut T. Kandemir
MICRO
1994
IEEE
85views Hardware» more  MICRO 1994»
13 years 11 months ago
A high-performance microarchitecture with hardware-programmable functional units
This paper explores a novel way to incorporate hardware-programmable resources into a processor microarchitecture to improve the performance of general-purpose applications. Throu...
Rahul Razdan, Michael D. Smith
JCIT
2007
63views more  JCIT 2007»
13 years 7 months ago
Optimizing Reaching Definitions Overhead in Queue Processors
Queue computers are a viable option for embedded systems design. Queue computers feature a dense instruction set, high parallelism, low hardware complexity. In this paper we propo...
Yuki Nakanishi, Arquimedes Canedo, Ben A. Abderaze...
CGO
2010
IEEE
14 years 2 months ago
Integrated instruction selection and register allocation for compact code generation exploiting freeform mixing of 16- and 32-bi
For memory constrained embedded systems code size is at least as important as performance. One way of increasing code density is to exploit compact instruction formats, e.g. ARM T...
Tobias J. K. Edler von Koch, Igor Böhm, Bj&ou...