Sciweavers

1304 search results - page 99 / 261
» RTOS Modeling for System Level Design
Sort
View
ETS
2007
IEEE
91views Hardware» more  ETS 2007»
15 years 10 months ago
PPM Reduction on Embedded Memories in System on Chip
This paper summarizes advanced test patterns designed to target dynamic and time-related faults caused by new defect mechanisms in deep-submicron memory technologies. Such tests a...
Said Hamdioui, Zaid Al-Ars, Javier Jiménez,...
CASES
2006
ACM
15 years 8 months ago
Incremental elaboration for run-time reconfigurable hardware designs
We present a new technique for compiling run-time reconfigurable hardware designs. Run-time reconfigurable embedded systems can deliver promising benefits over implementations in ...
Arran Derbyshire, Tobias Becker, Wayne Luk
ACSD
2006
IEEE
102views Hardware» more  ACSD 2006»
15 years 6 months ago
Models of Computation for Networks on Chip
Networks on chip platforms offer the opportunity to introduce a new abstraction level that defines a set of platform services with performance and power characteristics. By making...
Axel Jantsch
COMPSAC
2010
IEEE
15 years 2 months ago
A Consistency Model for Identity Information in Distributed Systems
In distributed IT systems, replication of information is commonly used to strengthen the fault tolerance on a technical level or the autonomy of an organization on a business level...
Thorsten Höllrigl, Jochen Dinger, Hannes Hart...
COMPUTER
2002
103views more  COMPUTER 2002»
15 years 4 months ago
SimpleScalar: An Infrastructure for Computer System Modeling
tail defines the level of abstraction used to implement the model's components. A highly detailed model will faithfully simulate all aspects of machine operation, whether or n...
Todd M. Austin, Eric Larson, Dan Ernst