PPM Reduction on Embedded Memories in System on Chip

This paper summarizes advanced test patterns designed to target dynamic and time-related faults caused by new defect mechanisms in deep-submicron memory technologies. Such tests are industrially evaluated together with the traditional tests at ”Design of Systems on Silicon (DS2)” in Spain in order to (a) validate the used fault models and (b) investigate the added value of the new tests and their impact on the PPM level. The preliminary silicon results are presented and analyzed. They validate some of the new dynamic fault models and show the importance of considering dynamic faults for high outgoing product quality. Key words: memory testing, static faults, dynamic faults, PPM reduction.

• Type: Conference
• Year: 2007
• Where: ETS
• Authors: Said Hamdioui, Zaid Al-Ars, Javier Jiménez, Jose Calero
• Keywords: Dynamic Faults, ETS 2007, Fault Models, Faults, Hardware