33 search results - page 4 / 7 » Rate Optimal VLSI Design from Data Flow Graph |
INFOCOM
2012
IEEE
11 years 9 months ago
2012
IEEE
—Power optimization has become a key challenge in the design of large-scale enterprise data centers. Existing research efforts focus mainly on computer servers to lower their ene...
INFOCOM
2008
IEEE
14 years 1 months ago
2008
IEEE
—In an n-way broadcast application each one of n overlay nodes wants to push its own distinct large data file to all other n-1 destinations as well as download their respective ...
FCCM
2006
IEEE
14 years 1 months ago
2006
IEEE
Field-Programmable Gate Arrays (FPGAs) are being employed in high performance computing systems owing to their potential to accelerate a wide variety of long-running routines. Par...
ASPDAC
2005
ACM
14 years 29 days ago
2005
ACM
– Reducing power consumption through high-level synthesis has attracted a growing interest from researchers due to its large potential for power reduction. In this work we study ...
BMCBI
2010
13 years 7 months ago
2010
Background: High throughput sequencing (HTS) platforms produce gigabases of short read (<100 bp) data per run. While these short reads are adequate for resequencing application...