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IWSOC
2003
IEEE
132views Hardware» more  IWSOC 2003»
14 years 29 days ago
A Catalog of Hardware Acceleration Techniques for Real-Time Reconfigurable System on Chip
The new technology of reconfigurable System-on-Chip is shown to be a good match to the requirements of realtime embedded systems. In particular, the judicious use of specialised d...
Neil W. Bergmann, Peter Waldeck, John A. Williams
COLT
1993
Springer
13 years 11 months ago
Bounding the Vapnik-Chervonenkis Dimension of Concept Classes Parameterized by Real Numbers
The Vapnik-Chervonenkis (V-C) dimension is an important combinatorial tool in the analysis of learning problems in the PAC framework. For polynomial learnability, we seek upper bou...
Paul W. Goldberg, Mark Jerrum
PDPTA
2003
13 years 9 months ago
Quaternary Arithmetic Logic Unit on a Programmable Logic Device
Common binary arithmetic operations such as addition/subtraction and multiplication suffer from O(n) carry propagation delay where n is the number of digits. Carry lookahead helps...
Songpol Ongwattanakul, Phaisit Chewputtanagul, Dav...
ERSA
2008
145views Hardware» more  ERSA 2008»
13 years 9 months ago
Multicore Devices: A New Generation of Reconfigurable Architectures
For two decades, reconfigurable computing systems have provided an attractive alternative to fixed hardware solutions. Reconfigurable computing systems have demonstrated the low c...
Steven A. Guccione
GIS
2005
ACM
14 years 8 months ago
Use of rational numbers in the design of robust geometric primitives for three-dimensional spatial database systems
A necessary step in the implementation of three-dimensional spatial data types for spatial database systems and GIS is the development of robust geometric primitives. The authors ...
Brian E. Weinrich, Markus Schneider