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» Reasoning about Memory Layouts
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APLAS
2008
ACM
13 years 11 months ago
Certified Reasoning in Memory Hierarchies
Abstract. Parallel programming is rapidly gaining importance as a vector to develop high performance applications that exploit the improved capabilities of modern computer architec...
Gilles Barthe, César Kunz, Jorge Luis Sacch...
ACSAC
2009
IEEE
14 years 4 months ago
Surgically Returning to Randomized lib(c)
—To strengthen systems against code injection attacks, the write or execute only policy (W⊕X) and address space layout randomization (ASLR) are typically used in combination. T...
Giampaolo Fresi Roglia, Lorenzo Martignoni, Robert...
PPOPP
2003
ACM
14 years 3 months ago
Compactly representing parallel program executions
Collecting a program’s execution profile is important for many reasons: code optimization, memory layout, program debugging and program comprehension. Path based execution pro...
Ankit Goel, Abhik Roychoudhury, Tulika Mitra
CORR
2011
Springer
222views Education» more  CORR 2011»
13 years 1 months ago
A New Data Layout For Set Intersection on GPUs
Abstract—Set intersection is the core in a variety of problems, e.g. frequent itemset mining and sparse boolean matrix multiplication. It is well-known that large speed gains can...
Rasmus Resen Amossen, Rasmus Pagh
DATE
2006
IEEE
106views Hardware» more  DATE 2006»
14 years 3 months ago
Memory centric thread synchronization on platform FPGAs
Concurrent programs are difficult to write, reason about, re-use, and maintain. In particular, for system-level ions that use a shared memory abstraction for thread or process syn...
Chidamber Kulkarni, Gordon J. Brebner