174 search results - page 11 / 35 » Reclocking for high-level synthesis |
DATE
1998
IEEE
13 years 11 months ago
1998
IEEE
This paper presents a new approach to cross-level hierarchical high-level synthesis. A methodology is presented, that supports the efficient synthesis of hierarchical specified sy...
ISLPED
1997
ACM
13 years 11 months ago
1997
ACM
With the increasing performance and density of VLSI circuits as well as the popularity of portable devices such as personal digital assistance, power consumption has emerged as an...
ICCD
1992
IEEE
13 years 11 months ago
1992
IEEE
Current synthesis methodologies based on hardwaredescription languages focus mainly on two distinct levels: behavior and register-transfer levels. In many practical cases, however...
FPL
2006
Springer
13 years 11 months ago
2006
Springer
This paper presents preliminary work exploring adaptive field programmable gate arrays (AFPGAs). An AFPGA is adaptative in the sense that the functionality of subcircuits placed o...
CORR
2006
Springer
13 years 7 months ago
2006
Springer
We introduce a new approach to take into account the memory architecture and the memory mapping in the High- Level Synthesis of Real-Time embedded systems. We formalize the memory...