68 search results - page 14 / 14 » Reconfigurable Processing Units vs. Reconfigurable Interconn... |
MICRO
2010
IEEE
13 years 7 months ago
2010
IEEE
Single-thread performance, reliability and power efficiency are critical design challenges of future multicore systems. Although point solutions have been proposed to address thes...
ISCAS
2007
IEEE
14 years 4 months ago
2007
IEEE
—In this paper, we propose a high speed adder which is adopted for our reconfigurable architecture called FleXilicon. To support sub-word parallelism, the FleXilicon architecture...
IPPS
2007
IEEE
14 years 4 months ago
2007
IEEE
In this paper we present a cost-effective, high bandwidth server I/O network architecture, named PaScal (Parallel and Scalable). We use the PaScal server I/O network to support da...