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FPGA
2010
ACM
232views FPGA» more  FPGA 2010»
13 years 8 months ago
High-throughput bayesian computing machine with reconfigurable hardware
We use reconfigurable hardware to construct a high throughput Bayesian computing machine (BCM) capable of evaluating probabilistic networks with arbitrary DAG (directed acyclic gr...
Mingjie Lin, Ilia Lebedev, John Wawrzynek
ASAP
2008
IEEE
167views Hardware» more  ASAP 2008»
14 years 2 months ago
Extending the SIMPPL SoC architectural framework to support application-specific architectures on multi-FPGA platforms
Process technology has reduced in size such that it is possible to implement complete applicationspecific architectures as Systems-on-Chip (SoCs) using both Application-Specific I...
David Dickin, Lesley Shannon
ICIP
2004
IEEE
14 years 9 months ago
H.264/AVC data partitioning for mobile video communication
In this work we compare non-scalable video coding with data partitioning using H.264/AVC under similar application and channel constraints for conversational applications over mob...
Thomas Stockhammer, Maja Bystrom
COMSIS
2007
167views more  COMSIS 2007»
13 years 8 months ago
Developing a New Color Model for Image Analysis and Processing
The theoretical outcomes and experimental results of new color model implemented in algorithms and software of image processing are presented in the paper. This model, as it will b...
Rashad J. Rasras, Ibrahiem M. M. El Emary, Dimitri...
ICIP
1995
IEEE
14 years 9 months ago
Parallel programmable video co-processor design
Modern video applications call for computationally intensive data processing at very high data rate. In order to meet the high-performance/low-cost constraints, the stateof-the-ar...
An-Yeu Wu, K. J. Ray Liu, Arun Raghupathy, Shang-C...