75 search results - page 3 / 15 » Reconfiguration for Fault Tolerance Using Graph Grammars |
TC
1998
13 years 8 months ago
1998
—The very high levels of integration and submicron device sizes used in current and emerging VLSI technologies for FPGAs lead to higher occurrences of defects and operational fau...
FPL
2006
Springer
14 years 7 days ago
2006
Springer
As manufacturing technology enters the ultra-deep submicron era, wafer yields are destined to drop due to higher occurrence of physical defects on the die. This paper proposes a y...
ENTCS
2002
13 years 8 months ago
2002
This paper presents a mechanism for dynamic reconfiguration of component-based applications and its fault tolerance strategy. The mechanism, named generic connector, allows compos...
ETFA
2006
IEEE
14 years 2 months ago
2006
IEEE
♦ To increase the amount of logic available to the users in SRAM-based FPGAs, manufacturers are using nanometric technologies to boost logic density and reduce costs, making its ...
HPCC
2009
Springer
13 years 6 months ago
2009
Springer
Domain-partition (DP) model is a general model for reliability maximization problem under given redundancy. In this paper, an improved DP model is used to formulate a reconfigurati...