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DAC
2005
ACM
14 years 7 months ago
Physically-aware HW-SW partitioning for reconfigurable architectures with partial dynamic reconfiguration
Many reconfigurable architectures offer partial dynamic configurability, but current system-level tools cannot guarantee feasible implementations when exploiting this feature. We ...
Sudarshan Banerjee, Elaheh Bozorgzadeh, Nikil D. D...
ICRA
2007
IEEE
160views Robotics» more  ICRA 2007»
14 years 1 months ago
Morphing Bus: A rapid deployment computing architecture for high performance, resource-constrained robots
— For certain applications, field robotic systems require small size for cost, weight, access, stealth or other reasons. Small size results in constraints on critical resources s...
Colin D'Souza, Byung Hwa Kim, Richard M. Voyles
MICRO
2010
IEEE
167views Hardware» more  MICRO 2010»
13 years 4 months ago
Erasing Core Boundaries for Robust and Configurable Performance
Single-thread performance, reliability and power efficiency are critical design challenges of future multicore systems. Although point solutions have been proposed to address thes...
Shantanu Gupta, Shuguang Feng, Amin Ansari, Scott ...
JHSN
2000
112views more  JHSN 2000»
13 years 6 months ago
A hierarchical Quality of Service control architecture for configurable multimedia applications
In order to achieve the best application-level Quality-of-Service (QoS), multimedia applications need to be dynamically tuned and reconfigured to adapt to fluctuating computing an...
Baochun Li, William Kalter, Klara Nahrstedt
DAC
2004
ACM
14 years 7 months ago
Defect tolerant probabilistic design paradigm for nanotechnologies
Recent successes in the development and self-assembly of nanoelectronic devices suggest that the ability to manufacture dense nanofabrics is on the near horizon. However, the trem...
Margarida F. Jacome, Chen He, Gustavo de Veciana, ...