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CODES
2010
IEEE
13 years 4 months ago
Automatic parallelization of embedded software using hierarchical task graphs and integer linear programming
The last years have shown that there is no way to disregard the advantages provided by multiprocessor System-on-Chip (MPSoC) architectures in the embedded systems domain. Using mu...
Daniel Cordes, Peter Marwedel, Arindam Mallik
CCO
2001
Springer
161views Combinatorics» more  CCO 2001»
13 years 11 months ago
Branch, Cut, and Price: Sequential and Parallel
Branch, cut, and price (BCP) is an LP-based branch and bound technique for solving large-scale discrete optimization problems (DOPs). In BCP, both cuts and variables can be generat...
Laszlo Ladányi, Ted K. Ralphs, Leslie E. Tr...
FCCM
2002
IEEE
321views VLSI» more  FCCM 2002»
13 years 11 months ago
Queue Machines: Hardware Compilation in Hardware
Abstract - In this paper, we hypothesize that reconfigurable computing is not more widely used because of the logistical difficulties caused by the close coupling of applications a...
Herman Schmit, Benjamin A. Levine, Benjamin Ylvisa...
CASES
2009
ACM
14 years 1 months ago
CGRA express: accelerating execution using dynamic operation fusion
Coarse-grained reconfigurable architectures (CGRAs) present an appealing hardware platform by providing programmability with the potential for high computation throughput, scalab...
Yongjun Park, Hyunchul Park, Scott A. Mahlke
IEEEPACT
2009
IEEE
14 years 1 months ago
Automatic Tuning of Discrete Fourier Transforms Driven by Analytical Modeling
—Analytical models have been used to estimate optimal values for parameters such as tile sizes in the context of loop nests. However, important algorithms such as fast Fourier tr...
Basilio B. Fraguela, Yevgen Voronenko, Markus P&uu...