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» Reducing Compilation Time Overhead in Compiled Simulators
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IEEECIT
2010
IEEE
13 years 6 months ago
CFCSS without Aliasing for SPARC Architecture
With the increasing popularity of COTS (commercial off the shelf) components and multi-core processor in space and aviation applications, software fault tolerance becomes attracti...
Chao Wang, Zhongchuan Fu, Hongsong Chen, Wei Ba, B...
ASPLOS
2010
ACM
14 years 3 months ago
Shoestring: probabilistic soft error reliability on the cheap
Aggressive technology scaling provides designers with an ever increasing budget of cheaper and faster transistors. Unfortunately, this trend is accompanied by a decline in individ...
Shuguang Feng, Shantanu Gupta, Amin Ansari, Scott ...
SIGPLAN
2002
13 years 7 months ago
Write barrier removal by static analysis
We present a new analysis for removing unnecessary write barriers in programs that use generational garbage collection. To our knowledge, this is the first static program analysis...
Karen Zee, Martin C. Rinard
INFOCOM
2012
IEEE
11 years 10 months ago
Robust multi-pipeline scheduling in low-duty-cycle wireless sensor networks
—Data collection is one of the major traffic pattern in wireless sensor networks, which requires regular source nodes to send data packets to a common sink node with limited end...
Yongle Cao, Shuo Guo, Tian He
LCPC
2005
Springer
14 years 1 months ago
Optimizing Packet Accesses for a Domain Specific Language on Network Processors
Programming network processors remains a challenging task since their birth until recently when high-level programming environments for them are emerging. By employing domain speci...
Tao Liu, Xiao-Feng Li, Lixia Liu, Chengyong Wu, Ro...