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» Reducing Compilation Time Overhead in Compiled Simulators
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RTAS
2003
IEEE
14 years 1 months ago
Collaborative Operating System and Compiler Power Management for Real-Time Applications
Managing energy consumption has become vitally important to battery operated portable and embedded systems. A dynamic voltage scaling (DVS) technique reduces the processor’s dyn...
Nevine AbouGhazaleh, Daniel Mossé, Bruce R....
ADAEUROPE
2005
Springer
14 years 1 months ago
The Application of Compile-Time Reflection to Software Fault Tolerance Using Ada 95
Transparent system support for software fault tolerance reduces performance in general and precludes application-specific optimizations in particular. In contrast, explicit support...
Patrick Rogers, Andy J. Wellings
ICCD
1993
IEEE
111views Hardware» more  ICCD 1993»
13 years 12 months ago
Ravel-XL: A Hardware Accelerator for Assigned-Delay Compiled-Code Logic Gate Simulation
Ravel-XL is a single-boardhardware accelerator for gate-level digital logic simulation. It uses a standard levelizedcode approach to statically schedule gate evaluations.However, u...
Michael A. Riepe, João P. Marques Silva, Ka...
IPPS
2007
IEEE
14 years 2 months ago
An Optimizing Compiler for Parallel Chemistry Simulations
Well designed domain specific languages enable the easy expression of problems, the application of domain specific optimizations, and dramatic improvements in productivity for t...
Jun Cao, Ayush Goyal, Samuel P. Midkiff, James M. ...
FPGA
2004
ACM
174views FPGA» more  FPGA 2004»
14 years 1 months ago
A compiled accelerator for biological cell signaling simulations
The simulation of large systems of biochemical reactions is a key part of research into molecular signaling and information processing in biological cells. However, it can be impr...
John F. Keane, Christopher Bradley, Carl Ebeling